Electroluminescent displays (ELDs) are advantageous by virtue of their low operating voltage with respect to cathode ray tubes, their superior image quality, wide viewing angle-and fast response time over liquid crystal displays, and their superior gray scale capability and thinner profile than plasma display panels.
An ELD has two intersecting sets of parallel electrically conductive address lines called rows and columns that are disposed on either side of a phosphor film encapsulated between two dielectric films. A pixel is defined as the intersection point between a row and a column. Each pixel is illuminated by the application of a voltage across the intersection of row and column.
Video-capable ELDs comprise a pixel array driven using passive matrix addressing. Each pixel includes of three sub-pixels to generate red, green and blue light for full colour. Each of the sub-pixels comprises a portion of the aforementioned thin phosphor film, disposed between the two insulator films that, in turn, are disposed between row and column address lines. Matrix addressing entails applying a voltage below the threshold voltage to a row while simultaneously applying a modulation voltage of the opposite polarity to each column that bisects that row in two. The voltages on the row and the column are summed to give a total voltage in accordance with the illumination desired on the respective sub-pixels, thereby generating one line of the image. An alternate scheme is to apply the maximum sub-pixel voltage to the row and apply a modulation voltage of the same polarity to the columns. The magnitude of the modulation voltage is up to the difference between the maximum voltage and the threshold voltage to set the pixel voltages in accordance with the desired image. In either case, once each row is addressed, another row is addressed in a similar manner until all of the rows have been addressed. Rows which are not addressed are left at open circuit.
The sequential addressing of all rows constitutes a complete frame. Typically a new frame is addressed at least about 50 times per second to generate what appears to the human eye a flicker-free video image.
ELDs may be constructed on a substrate by sequential deposition and patterning of a first parallel electrode array, an insulating layer, a luminescent layer, a second insulating layer and a second parallel electrode array substantially orthogonal to the first parallel electrode array. The layers of the display may be deposited and patterned using thick film techniques or thin film techniques. The displays are operated using passive matrix addressing, as described above.
Thick film dielectric ELDs have been found to have particular utility for high-resolution video-capable large area displays in television and other applications. These are constructed on ceramic, glass or glass ceramic substrates as exemplified by U.S. Pat. No. 5,432,015, PCT Patent Application CA00/00561 and PCT Patent Application CA02/01932. In particular, the first array of electrodes can be deposited on the substrate and patterned using vacuum deposition or by printing and sintering of thick film pastes containing electrically conductive powders. Typically, gold is used as the electrically conductive material for the first parallel array of electrodes, but other conductive metals, alloys, or electrically conductive materials may be used as well, provided that they are compatible with the rest of the display structure.
The second array of electrodes is typically indium tin oxide (ITO), which is optically transparent as well as electrically conductive to allow light generated within the display to be transmitted to the display viewer. The ITO is typically vacuum deposited on the display structure and patterned into parallel lines using photolithographic or laser patterning methods, as exemplified in PCT Patent Application CA02/01891. The ends of these indium tin oxide address lines overlap with and extend beyond the active area of the display to contact pads using gold as the electrical conductor.
Display drivers are provided that function as switches to supply the required voltage pulses to the rows and columns. These drivers are packaged as multiple output chips that can drive several rows or columns and are typically mounted on a separate circuit board. The outputs from the driver chips are connected to the rows and columns using flex-tape connectors comprising parallel electrical conductors embedded in a plastic tape. The conductors in the tape are aligned with conductor pads connected to the rows and columns on the display panel and also with the outputs from the driver chips on the circuit board. Electrical connections are formed by hot pressing the tape onto the respective conductor pads. However, in the manufacturing process it is desirable to electrically test the panel before making these connections so that defective panels can be discarded or repaired before the valuable circuit boards are attached to them.
Prior art method electrical testing of ELD panels includes identifying and locating short circuits (“shorts”) between adjacent rows and columns on the panel; identifying and locating electrical discontinuities (“opens”) along rows and columns; measuring the white luminance uniformity of the panel; and independently measuring the red, green and blue sub-pixel set uniformity.
The test methods of the prior art sometimes cause electrical breakdown between adjacent rows or between adjacent columns during the test procedure. This is due to the generation of large voltages between the rows or columns caused by sudden changes in the current passing through these components if the contacts made using the elastomeric strips are intermittent. The large voltages generated by these current changes may be characterized by the fundamental relationship V=L di/dt, where V is the induced voltage, di/dt is the rate of current change with time and L is the electrical inductance of the panel and associated electrical connections for the test. For an intermittent connection, the rate of current change is typically very high, resulting in a high induced voltage.
Accordingly, there is a need in the art for an improved method of conducting electrical testing of an ELD constructed on a substrate. Ideally, the method should provide improved testing reliability and avoid inadvertent damage to the display during testing due to intermittent electrical contacts.
The prior art has attempted to address this need, as follows:
Published U.S. 2003/137318 and U.S. 2003/0117165 both teach
the use of shorting bars for testing, but these are not formed as part of the panel manufacturing process and so do not provide reliable connections.
Published U.S. 2002/0063574 discloses shorting bars formed during fabrication of an LCD display, that are later trimmed off. However, all rows or columns are not tested together, and a large number of probes are required for the test.
U.S. Pat. No. 6,566,902 teaches parallel connection of data lines (i.e. columns) for an LCD display, but there is no requirement to disconnect the parallel connection following testing.
U.S. Pat. No. 6,111,424 discloses shorting bars fabricated on the panel during manufacture that are disconnected following testing of an active matrix LCD panel, with defect analysis performed by infrared imaging.
U.S. Pat. No. 6,028,442 arranges LCD data lines into a number of blocks using parallel connections controlled by thin film transistors.
U.S. Pat. No. 5,608,558 discloses shorting bars as part of a defect testing apparatus for active matrix LCD displays, which must be connected with a large number of connections to the panel.
All of the foregoing prior art relates to testing of LCD panels, mostly active matrix LCD panels, where the principle of operation is different from EL displays, and the detection method for shorts and opens is also different.
U.S. 2001/0019243 relates to EL displays, but does not address the need in the art for an improved method of conducting electrical testing of an ELD.